1. Field of the Invention
The present invention relates to a semiconductor device including a MOS transistor and a resistor.
2. Description of the Related Art
In an analog IC such as a voltage detector, the following measures are typically taken for obtaining desired characteristics for an output voltage. Fuses for laser trimming, which are formed of thin film resistors such as polycrystalline silicon, are disposed, and the fuses are selectively burned and cut by laser irradiation to adjust a combination pattern of the resistors, to thereby adjust fluctuations in characteristics caused by fluctuations at mass production in a wafer process, and adjust a target value of a circuit.
Referring to FIGS. 4 to 6, such a fuse for laser trimming in an analog IC is described. FIG. 4 is a top view, FIG. 5 is a schematic cross-sectional view taken along the cut line C-C′, and FIG. 6 is a schematic cross-sectional view taken along the cut line D-D′. In order that laser may irradiate a fuse 306 made of a thin film resistor of polycrystalline silicon, a nitride film 317 as a protective film and interlayer insulating films 313 and 315 provided across multi-layered wirings are partly etched to form an opening portion 318. Accordingly, the side walls of the nitride film and the interlayer insulating films in the fuse opening portion are exposed. In a double-metal process or a further multi-layered wiring process, a known technology for planarization is a technology of performing etch back after coating, for example, an SOG layer 314 made of spin-on glass (SOG). In the etch back technology, however, the SOG layer 314 is present between the laminated interlayer insulating films, and hence moisture may enter through the SOG layer to cause fluctuations in element characteristics of an IC, resulting in a problem in terms of long-term reliability. Particularly in a PMOS transistor, a threshold voltage shift of the transistor occurs due to negative bias temperature instability (NBTI), which occurs when a negative gate bias is applied under a high temperature state.
As a countermeasure against the degradation in long-term reliability caused by the entering of moisture from the fuse opening portion, for example, Japanese Patent Publication Nos. H05-63091 and H07-22508 disclose a countermeasure for preventing the entering of moisture by forming a guard ring with the use of a metal so as to be a barrier on the inner side of the IC with respect to the fuse opening portion.
Referring to FIGS. 5 and 6, the entering of moisture through the SOG layer is described. FIG. 5 illustrates the cross section along the fuse 306. That is, FIG. 5 illustrates the cross section including a fuse trimming laser irradiation portion 320 of FIG. 4. Above the fuse 306, a seal ring 319 is formed through the intermediation of an intermediate insulating film 311. The SOG layer 314 between first TEOS (313) and second TEOS (315) is exposed in the fuse opening portion 318 but is disconnected by the seal ring 319, and hence the SOG layer 314 is never connected to an SOG layer 314 provided inside the IC. On the other hand, FIG. 6 illustrates the cross section excluding the fuse trimming laser irradiation portion 320. In this cross section, the fuse 306 has only a portion corresponding to a fuse terminal portion 321, and the portion corresponding to the fuse trimming laser irradiation portion 320 does not appear in FIG. 6 but the intermediate insulating film 311 is deposited directly on an underlaying field insulating film 303. Accordingly the seal ring 319 is formed at a position lower than a first metal wiring 312, with the result that the SOG layer 314 between the first TEOS 313 and the second TEOS 315 crosses over the seal ring 319 to be connected to the SOG layer 314 provided inside the IC. Thus, moisture enters the inside of the IC.